Pins and Connections
3.2.6
Analog-to-digital conversion: AN0, AN1
The on-chip ADC can be used to perform a differential, analog-to-digital conversion based on the voltage
present across pins AN0(-) and AN1(+). Conversions on these pins are subject to the same output data rate
(ODR) rules as the MEMS transducer signals.
State at reset: Inactive. AN[1:0] are secondary functions on RGPIO[7:6], which owns the pins at reset.
3.2.7
Rapid General-Purpose I/O: RGPIO[9:0]
The ColdFire V1 CPU has a feature called “Rapid GPIO” (RGPIO). This is a 16-bit input/output port with
single-cycle write, set, clear and toggle functions available to the CPU. The MMA955xL platform brings
out the lower 10 bits of that port as pins of the device.
State at reset:
? RGPIO[9]: Inactive. BKGD/MS owns the pin at reset.
? RGPIO[8:2]: Pin mux registers for these bits are configured as RGPIO. Pull-ups are disabled.
RGPIO functionality can be enabled via RGPIO_ENB[8:2].
? RGPIO[1:0]: Inactive. SDA0 and SCL0 own the pin at reset.
3.2.8
Interrupts: INT
This input pin may be used to wake the CPU from a deep-sleep mode. It can be programmed to trigger on
either rising or falling edge or high or low level. This pin operates as a level-7 (high-priority) interrupt.
State at reset: Inactive. RGPIO[4] owns the pin at reset.
3.2.9
Debug/mode control: BKGD/MS
At power-up, this pin operates as Mode Select. If low during power-up, the CPU will boot into debug halt
mode. If high, the CPU will boot normally and run code.
After power-on reset, this pin can operate as a bidirectional, single-wire background debug port. It can be
used by development tools for downloading code into on-chip RAM and flash and to debug code.
State at reset: Mode Select (MS).
? MS = 0 at exit from reset => Boot to debug halt mode
? MS = 1 at exit from reset => Boot to run mode
State after reset: BKGD. The BKGD pin is a bidirectional, pseudo-open-drain pin used for
communications with a debug environment. For additional details, see “Version 1 ColdFire Debug” on
MMA955xL Intelligent, Motion-Sensing Platform Hardware Reference Manual, Rev. 1.0
Freescale Semiconductor, Inc.
29
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